1. Field of Invention
The present invention relates to semiconductor devices, and particularly to a semiconductor device which is provided with MOS transistors formed on a semiconductor layer on an insulating layer and which can prevent supporting substrate stray effects.
2. Description of Related Art
A silicon-on-insulator (SOI) technology, which includes forming a semiconductor layer of single-crystal silicon on an insulator and forming semiconductor devices such as transistor devices on the semiconductor layer, has advantages, such as high-speed device operation, reduced electrical power consumption, and high integration density, and may be applied to electro-optical devices, such as liquid crystal devices.
In typical bulk semiconductor components, a channel region of a MOS transistor is maintained at a predetermined potential by an underlying supporting substrate. Thus, a parasitic bipolar effect due to a change in potential of the channel region does not cause deterioration of electrical characteristics, such as breakdown voltage of the device.
In a MOS transistor having an SOI structure, however, a channel bottom section is completely separated by an underlying insulating film. Thus, the channel region cannot be maintained at a predetermined potential, and is in an electrically straying state. In such a state, excessive carriers are accumulated in the channel bottom section in which the excessive carriers are generated by impact ionization due to collision of carriers accelerated in an electric field in the vicinity of a drain region with crystal lattices. When the channel potential increases by the accumulation of the excessive carriers in the channel bottom section, the NPN structure (in the case of N-channel type) of the source/channel/drain operates as an apparent bipolar device and yields an extraordinary current which causes deterioration of the breakdown voltage between the source and the drain, and thus, deterioration of electrical characteristics of the device. A series of phenomena caused by an electrical straying state of the channel region is called a supporting substrate stray effect.
A conventional method for suppressing the supporting substrate stray effect is providing a body contact region which is electrically connected to the channel region via a predetermined path in order to extract the excessive carriers in the channel region from the body contact region.
A semiconductor device including MOS transistors of an SOI structure having such a body contact region is disclosed in Japanese Unexamined Patent Application Publication No. 9-246562 (hereinafter Citation 1).
In a medium-breakdown-voltage MOS transistor used at approximately 15 volts in electro-optical devices such as liquid crystal devices, a semiconductor gate array including a plurality of the medium-breakdown-voltage MOS transistors, and a semiconductor device including a plurality of the medium-breakdown-voltage MOS transistors connected to each other in series, a high drain electric field generates a large amount of excessive carriers. Effective extraction of the excessive carriers is performed by increasing the impurity concentration in the extraction region to decrease the resistance of the extraction region. When the impurity concentration is increased in the structure of the Citation 1, the PN junctions between the extraction region and source/drain regions cannot withstand a high drive voltage.
It is an object of the present invention, for at least solving the above problems, to provide a semiconductor device provided with a MOS transistor formed on a semiconductor layer on an insulating layer which has junctions between the extraction region and the source/drain regions exhibiting a high breakdown voltage.
It is another object of the present invention to provide a semiconductor gate array including a plurality of the MOS transistors arranged on the semiconductor layer on the insulating layer.
It is another object of the present invention to provide a semiconductor device including a plurality of the MOS transistors which are formed on the semiconductor layer on the insulating layer and are connected to each other in series.
In an exemplary embodiment of the present invention, a semiconductor device preferably consists of a supporting substrate having insulation at least at a surface thereof, a semiconductor layer formed on the surface of the supporting substrate, and a MOS transistor formed in the semiconductor layer. The MOS transistor preferably consists of a channel region of a first conductive type formed on the surface of the supporting substrate, a source region and a drain region of a second conductive type formed on the surface of the supporting substrate so as to sandwich the channel region, an second insulating layer formed on the channel region, and an electrode formed on the insulating layer. The semiconductor device may further consist of a first semiconductor region provided on the surface of the supporting substrate at least at one end in the channel width direction of at least one of the source region and the drain region along the channel length direction, and a second semiconductor region of the first conductive type provided on the surface of the supporting substrate so as to sandwich the first semiconductor region by the source region or the drain region along the first semiconductor region. The second semiconductor region preferably has an impurity concentration which is higher than that in the channel region, and the first semiconductor region preferably has an impurity concentration which is lower than that in the source region and the drain region and is lower than that in the second semiconductor region.
According to this configuration of this exemplary embodiment of the present invention, the first semiconductor region having a low impurity concentration is provided between the second semiconductor region which is an extracting region of excessive carriers and the source and drain regions to suppress the gradient of the impurity concentrations between the second semiconductor region and the source and drain regions. Thus, the breakdown voltage of the junctions between the second semiconductor region and the source and drain regions may be maintained at a high level.
In another exemplary embodiment of the present invention, in the semiconductor device, the first semiconductor region may be a semiconductor of the second conductive type and may have an impurity concentration which is lower than that in the source region and the drain region.
According to this configuration of this exemplary embodiment of the present invention, the first semiconductor region of the second conductive type having a low impurity concentration is provided between the second semiconductor region as an extracting region of the excessive carriers and the source and drain regions. Thus, the breakdown voltage of the junctions between the second semiconductor region and the source and drain regions may be maintained at a high level.
In another exemplary embodiment of the present invention, in the semiconductor device, the first semiconductor region may be a semiconductor of the first conductive type, and may have an impurity concentration which is lower than that in the second semiconductor region.
According to this configuration of this exemplary embodiment of the present invention, the first semiconductor region of the first conductive type having a low impurity concentration is provided between the second semiconductor region as an extracting region of the excessive carriers and the source and drain regions. Thus, the breakdown voltage of the junctions between the second semiconductor region and the source and drain regions may be maintained at a high level.
In another exemplary embodiment of the present invention, in the semiconductor device, the first semiconductor region may be a semiconductor of the first conductive type, and may have an impurity concentration which is substantially the same as that in the channel region.
According to this configuration of this exemplary embodiment of the present invention, the first semiconductor region may be formed by the same step for implanting an impurity into the channel region without an additional step.
In another exemplary embodiment of the present invention, in the semiconductor device, the first semiconductor region may substantially not be doped with an impurity.
According to this configuration of this exemplary embodiment of the present invention, the first semiconductor region, which is substantially not doped with an impurity, may be provided between the second semiconductor region which is an extracting region of excessive carriers and the source and drain regions to at least suppress the gradient of the impurity concentrations between the second semiconductor region and the source and drain regions. Thus, the breakdown voltage of the junctions between the second semiconductor region and the source and drain regions may be maintained at a high level.
In another exemplary embodiment of the present invention, in the semiconductor device, an LDD region of the second conductive type may be formed between the channel region and the source region and between the channel region and drain region, and the first semiconductor region may be a semiconductor of the second conductive type and may have an impurity concentration which is substantially the same as that in the LDD region.
According to this configuration of this exemplary embodiment of the present invention, the first semiconductor region may be formed by the same step for implanting an impurity into the LDD region without an additional step.
In another exemplary embodiment of the present invention, in the semiconductor device, an LDD region of the second conductive type may be formed between the channel region and the source region and between the channel region and drain region, and the first semiconductor region may be a semiconductor of the first conductive type and may have an impurity concentration which is substantially the same as that in an LDD region formed in a MOS transistor complementing a MOS transistor of the conductive type which is the same as that of the channel region.
According to this configuration of this exemplary embodiment of the present invention, the first semiconductor region may be formed by the same step for implanting an impurity into the LDD region without an additional step.
In another exemplary embodiment of the present invention, in the semiconductor device, the supporting substrate having insulation at least at a surface thereof preferably consists of a base substrate and an insulating layer formed on the base substrate.
Also, in another exemplary embodiment of the present invention, in the semiconductor device, the base substrate preferably consists of single-crystal silicon.
According to these configurations of the above exemplary embodiments of the present invention, the semiconductor device may be used as a device substrate for an electro-optical device, such as a reflective liquid crystal device. Moreover, a bulk silicon device may be used without modification.
In another exemplary embodiment of the present invention, in the semiconductor device, the base substrate preferably consists of quartz, and the semiconductor layer formed on the insulating layer of the supporting substrate preferably consists of single-crystal silicon.
Since the base substrate is transparent in this configuration of this exemplary embodiment of the present invention, the semiconductor device may be used as a device substrate for a transmissive electro-optical device, such as a liquid crystal device. This base substrate allows a high-temperature processing which is not applicable to glass, and thus a high-quality insulating film and the like may be provided and the device is highly reliable. Since the semiconductor layer is composed of single-crystal silicon, a high-quality, high-definition electro-optical device with a high drive frequency may be obtained.
In another exemplary embodiment of the present invention, in the semiconductor device, the base substrate preferably consists of quartz, and the semiconductor layer formed on the insulating layer of the supporting substrate preferably consists of polycrystalline silicon.
Since the base substrate is transparent in this configuration of this exemplary embodiment of the present invention, the semiconductor device may be used as a device substrate for a transmissive electro-optical device, such as a liquid crystal device. This base substrate allows a high-temperature processing which is not applicable to glass, and thus a high-quality insulating film and the like may be provided and the device is highly reliable. Since the semiconductor layer may be composed of polycrystalline silicon, the layer may be readily formed on the base substrate and a high-quality, high-definition electro-optical device with a high drive frequency may be obtained.
In another exemplary embodiment of the present invention, in the semiconductor device, the base substrate preferably consists of glass.
Since the base substrate is an inexpensive transparent supporting substrate in this configuration of this exemplary embodiment of the present invention, a device substrate for a transmissive electro-optical device, such as a liquid crystal device, may be provided at reduced cost.
In another exemplary embodiment of the present invention, a semiconductor gate array preferably consists of a supporting substrate having insulation at least at a surface thereof, a semiconductor layer formed on the surface of the supporting substrate, and a plurality of MOS transistors formed in the semiconductor layer. Each of the MOS transistors preferably consists of a channel region of a first conductive type formed on the surface of the supporting substrate, a source region and a drain region of a second conductive type formed on the surface of the supporting substrate so as to sandwich the channel region, an insulating layer formed on the channel region, and an electrode formed on the insulating layer. The semiconductor gate array may further consist of a first semiconductor region provided on the surface of the supporting substrate at least at one end in the channel width direction of at least one of the source region and the drain region along the channel length direction, and a second semiconductor region of the first conductive type provided on the surface of the supporting substrate so as to sandwich the first semiconductor region by the source region or the drain region along the first semiconductor region. The second semiconductor region preferably has an impurity concentration which is higher than that in the channel region, and the first semiconductor region preferably has an impurity concentration which is lower than that in the source region and the drain region and is lower than that in the second semiconductor region.
According to this configuration of this exemplary embodiment of the present invention, also in the semiconductor gate array including the plurality of MOS transistors, the first semiconductor region having a low impurity concentration is provided between the second semiconductor region which is an extracting region of excessive carriers and the source and drain regions. Thus, the breakdown voltage of the junctions between the second semiconductor region and the source and drain regions may be maintained at a high level.
In another exemplary embodiment of the present invention, in the semiconductor gate array, the first semiconductor region of each MOS transistor may be a semiconductor of the second conductive type, and may have an impurity concentration which is lower than that in the source region, and the drain region.
According to this configuration of this exemplary embodiment of the present invention, also in the semiconductor gate array including the plurality of MOS transistors, the first semiconductor region of the second conductive type having a low impurity concentration is provided between the second semiconductor region as an extracting region of the excessive carriers and the source and drain regions. Thus, the breakdown voltage of the junctions between the second semiconductor region and the source and drain regions may be maintained at a high level.
In another exemplary embodiment of the present invention, in the semiconductor gate array, the first semiconductor region of each MOS transistor may be a semiconductor of the first conductive type, and may have an impurity concentration which is lower than that in the second semiconductor region.
According to this configuration of this exemplary embodiment of the present invention, also in the semiconductor gate array including the plurality of MOS transistors, the first semiconductor region of the first conductive type having a low impurity concentration is provided between the second semiconductor region as an extracting region of the excessive carriers and the source and drain regions. Thus, the breakdown voltage of the junctions between the second semiconductor region and the source and drain regions may be maintained at a high level.
In another exemplary embodiment of the present invention, in the semiconductor gate array, the first semiconductor region of each MOS transistor may be a semiconductor of the first conductive type, and may have an impurity concentration which is substantially the same as that in the channel region.
According to this configuration of this exemplary embodiment of the present invention, the first semiconductor region may be formed by the same step for implanting an impurity into the channel region without an additional step.
In another exemplary embodiment of the present invention, in the semiconductor gate array, the first semiconductor region of each MOS transistor may be substantially not be doped with an impurity.
According to this configuration of this exemplary embodiment of the present invention, also in the semiconductor gate array including the plurality of MOS transistors, the first semiconductor region, which is substantially not doped with an impurity, is provided between the second semiconductor region which is an extracting region of excessive carriers and the source and drain regions. Thus, the breakdown voltage of the junctions between the second semiconductor region and the source and drain regions may be maintained at a high level.
In another exemplary embodiment of the present invention, in the semiconductor gate array, an LDD region of the second conductive type may be formed between the channel region and the source region and between the channel region and drain region, and the first semiconductor region of each MOS transistor may be a semiconductor of the second conductive type and may have an impurity concentration which is substantially the same as that in the LDD region.
According to this configuration of this exemplary embodiment of the present invention, the first semiconductor region may be formed by the same step for implanting an impurity into the LDD region without an additional step.
In another exemplary embodiment of the present invention, in the semiconductor gate array, an LDD region of the second conductive type may be formed between the channel region and the source region and between the channel region and drain region, and the first semiconductor region of each MOS transistor may be a semiconductor of the first conductive type and may have an impurity concentration which is substantially the same as that in an LDD region formed in a MOS transistor complementing a MOS transistor of the conductive type which is the same as that of the channel region.
According to this configuration of this exemplary embodiment of the present invention, the first semiconductor region may be formed by the same step for implanting an impurity into the LDD region without an additional step.
In another exemplary embodiment of the present invention, in the semiconductor gate array, the supporting substrate having insulation at least at a surface thereof preferably consists of a base substrate and an insulating layer formed on the base substrate.
In another exemplary embodiment of the present invention, in the semiconductor device, the base substrate preferably consists of a single-crystal silicon.
According to these configurations of the above exemplary embodiments of the present invention, the semiconductor gate array may be used as a device substrate for an electro-optical device, such as a reflective liquid crystal device. Moreover, a bulk silicon device may be used without modification.
In another exemplary embodiment of the present invention, in the semiconductor gate array, the base substrate preferably consists of quartz, and the semiconductor layer formed on the insulating layer preferably consists of single-crystal silicon.
Since the base substrate is transparent in this configuration of this exemplary embodiment of the present invention, the semiconductor gate array may be used as a device substrate for a transmissive electro-optical device, such as a liquid crystal device. This base substrate allows a high-temperature processing which may be not applicable to glass, and thus a high-quality insulating film and the like may be provided and the device is highly reliable. Since the semiconductor layer is composed of single-crystal silicon, a high-quality, high-definition electro-optical device with a high drive frequency may be obtained.
In another exemplary embodiment of the present invention, in the semiconductor gate array, the base substrate preferably consists of quartz, and the semiconductor layer formed on the insulating layer comprises polycrystalline silicon.
Since the base substrate is transparent in this configuration of this exemplary embodiment of the present invention, the semiconductor gate array may be used as a device substrate for a transmissive electro-optical device, such as a liquid crystal device. This base substrate allows a high-temperature processing which may be not applicable to glass, and thus a high-quality insulating film and the like may be provided and the device is highly reliable. Since the semiconductor layer is composed of polycrystalline silicon, the layer may be readily formed on the base substrate and a high-quality, high-definition electro-optical device with a high drive frequency may be obtained.
In another exemplary embodiment of the present invention, in the semiconductor gate array, the base substrate preferably consists of glass.
Since the base substrate is an inexpensive transparent supporting substrate in this configuration of this exemplary embodiment of the present invention, a device substrate for a transmissive electro-optical device, such as a liquid crystal device, may be provided at reduced cost.
In another exemplary embodiment of the present invention, the semiconductor device preferably consists of a supporting substrate having insulation at least at a surface thereof, a semiconductor layer formed on the surface of the supporting substrate, and a plurality of MOS transistors formed in the semiconductor layer and connected to each other in series. Each of the MOS transistors preferably consists of a channel region of a first conductive type formed on the surface of the supporting substrate, a source region and a drain region of a second conductive type formed on the surface of the supporting substrate so as to sandwich the channel region, an insulating layer formed on the channel region, and an electrode formed on the second insulating layer. The semiconductor device may further consist of a first semiconductor region provided on the surface of the supporting substrate at least at one end in the channel width direction of one of the source region and the drain region along the channel length direction, which is not directly connected to an electrical power source, and a second semiconductor region of the first conductive type provided on the surface of the supporting substrate so as to sandwich the first semiconductor region by the source region or the drain region along the first semiconductor region. The semiconductor device may further consist of a third semiconductor region of the first conductive type provided on the surface of the supporting substrate at least at one end in the channel width direction of one of the source region and the drain region along the source region and the drain region, which may be directly connected to the electrical power source. Each of the second semiconductor region and the third semiconductor region has an impurity concentration which is higher than that in the channel region, and the first semiconductor region has an impurity concentration which is lower than that in the source region and the drain region and is lower than that in the second semiconductor region.
According to this exemplary configuration of this exemplary embodiment, also in the semiconductor device provided with the plurality of MOS transistors, which are connected in series, as used in a logic circuit, the first semiconductor region having a low impurity concentration is provided between the second semiconductor region as an extracting region of the excessive carriers and the source and drain regions so as to suppress the gradient of the impurity concentrations between the second semiconductor region and the source region. Thus, the breakdown voltage of the junction between the second semiconductor region and the source region may be maintained at a high level. In addition, the first semiconductor region is provided only in the source region of each MOS transistor which may be not directly connected to the electrical power source, and thus the semiconductor device exhibits low resistance.
In another exemplary embodiment of the present invention, in the semiconductor device, the first semiconductor region may be a semiconductor of the second conductive type, and may have an impurity concentration which may be lower than that in the source region and the drain region.
According to this configuration of this exemplary embodiment of the present invention, the semiconductor device having the plurality of MOS transistors connected in series includes the first semiconductor region of the second conductive type having a low impurity concentration which is provided between the second semiconductor region as an extracting region of the excessive carriers and the source and drain regions. Thus, the breakdown voltage of the junction between the second semiconductor region and the source region may be maintained at a high level.
In another exemplary embodiment of the present invention, in the semiconductor device, the first semiconductor region may be a semiconductor of the first conductive type, and may have an impurity concentration which may be lower than that in the second semiconductor region.
According to this configuration of this exemplary embodiment of the present invention, the semiconductor device having the plurality of MOS transistors connected in series includes the first semiconductor region of the first conductive type having a low impurity concentration which is provided between the second semiconductor region as an extracting region of the excessive carriers and the source and drain regions. Thus, the breakdown voltage of the junction between the second semiconductor region and the source region may be maintained at a high level.
In another exemplary embodiment of the present invention, in the semiconductor device, the first semiconductor region may be a semiconductor of the first conductive type, and may have an impurity concentration which may be substantially the same as that in the channel region.
According to this configuration of this exemplary embodiment of the present invention, the first semiconductor region may be formed by the same step for implanting an impurity into the channel region without an additional step.
In another exemplary embodiment of the present invention, in the semiconductor device, the first semiconductor region may be substantially not be doped with an impurity.
According to this configuration of this exemplary embodiment of the present invention, the semiconductor device having the plurality of MOS transistors connected in series includes the first semiconductor region substantially not doped with an impurity which is provided between the second semiconductor region as an extracting region of the excessive carriers and the source and drain regions. Thus, the breakdown voltage of the junction between the second semiconductor region and the source region may be maintained at a high level.
In another exemplary embodiment of the present invention, in the semiconductor device, an LDD region of the second conductive type may be formed between the channel region and the source region and between the channel region and drain region, and the first semiconductor region may be a semiconductor of the second conductive type and may have an impurity concentration which may be substantially the same as that in the LDD region.
According to this configuration of this exemplary embodiment of the present invention, the first semiconductor region may be formed by the same step for implanting an impurity into the LDD region without an additional step.
In another exemplary embodiment of the present invention, in the semiconductor device, an LDD region of the second conductive type may be formed between the channel region and the source region and between the channel region and drain region, and the first semiconductor region may be a semiconductor of the first conductive type and may have an impurity concentration which may be substantially the same as that in an LDD region formed in a MOS transistor complementing a MOS transistor of the conductive type which may be the same as that of the channel region.
According to this configuration of this exemplary embodiment of the present invention, the first semiconductor region may be formed by the same step for implanting an impurity into the LDD region without an additional step.
In another exemplary embodiment of the present invention, in the semiconductor device, the supporting substrate having insulation at least at a surface thereof preferably consists of a base substrate and an insulating layer formed on the base substrate.
In another exemplary embodiment of the present invention, in the semiconductor device, the base substrate preferably consists of single-crystal silicon.
According to these configurations of the above exemplary embodiments of the present invention, the semiconductor device may be used as a device substrate for an electro-optical device, such as a reflective liquid crystal device. Moreover, a bulk silicon device may be used without modification.
In another exemplary embodiment of the present invention, in the semiconductor device, the base substrate preferably consists of quartz, and the semiconductor layer formed on the insulating layer of the supporting substrate preferably consists of single-crystal silicon.
Since the base substrate is transparent in this configuration of this exemplary embodiment of the present invention, the semiconductor device may be used as a device substrate for a transmissive electro-optical device, such as a liquid crystal device. This base substrate allows a high-temperature processing which is not applicable to glass, and thus a high-quality insulating film and the like may be provided and the device is highly reliable. Since the semiconductor layer may be composed of single-crystal silicon, a high-quality, high-definition electro-optical device with a high drive frequency may be obtained.
In another exemplary embodiment of the present invention, in the semiconductor device, the base substrate preferably consists of quartz, and the semiconductor layer formed on the insulating layer of the supporting substrate preferably consists of polycrystalline silicon.
Since the base substrate is transparent in this configuration of this exemplary embodiment of the present invention, the semiconductor device may be used as a device substrate for a transmissive electro-optical device, such as a liquid crystal device. This base substrate allows a high-temperature processing which is not applicable to glass, and thus a high-quality insulating film and the like may be provided and the device is highly reliable. Since the semiconductor layer may be composed of polycrystalline silicon, the layer may be readily formed on the base substrate and a high-quality, high-definition electro-optical device with a high drive frequency may be obtained.
In another exemplary embodiment of the present invention, in the semiconductor device, the base substrate preferably consists of glass.
Since the base substrate is an inexpensive transparent supporting substrate in this configuration of the present invention, a device substrate for a transmissive electro-optical device, such as a liquid crystal device, may be provided at reduced cost.
In another exemplary embodiment of the present invention, an electro-optical device may consist of a supporting substrate constituting any one of the above semiconductor device, the above semiconductor gate array, and the above semiconductor device, another supporting substrate facing a semiconductor layer formed on a insulating layer on the supporting substrate, and a liquid crystal disposed between these two supporting substrates and driven by transistor elements in the semiconductor layer.
In another exemplary embodiment of the present invention, in the electronic equipment may consist of a light source, the above electro-optical device for modulating light incident on the light source in response to image information, and a projection device for projecting the light modulated by the electro-optical device.